(1) Field of the Invention
The present invention relates to a thin film transistor, a method of producing the thin film transistor, a thin film transistor array substrate using the thin film transistor, and display devices using the thin film transistor array substrate such as a liquid crystal display device and an electroluminescent display device. More particularly, the invention relates to a thin film transistor having a channel region, a source region, and a drain region, the source and drain regions having a low melting point region composed of a semiconductor having a melting point lower than that of the semiconductor in the channel region, and relates to fabrication methods and applications of the thin film transistor.
(2) Description of the Prior Art
The escalating demands for increased performance in electronic appliances employing thin film transistors (hereafter, also abbreviated as TFTs) require further scaling down of the sizes, higher response speed, and lower power consumption in the TFTs. The requirements are particularly strong in TFTs for use in display devices, such as active matrix driven liquid crystal display devices. In order to meet these requirements, it is necessary that a thin film transistor having a channel region with a short channel length and a short channel width be driven at low voltage.
Conventionally, the channel region, the source region, and the drain region in a thin film transistor are formed of the same kind of semiconductor. Amorphous silicon thin film transistors (a-Si TFTs) and polycrystalline silicon thin film transistors (p-Si TFTs), in which those regions are formed of amorphous silicon thin film and polycrystalline silicon thin film, respectively, are well known in the art. In addition, polycrystalline silicon germanium thin film transistors (p-SiGe TFT) have been disclosed in Japanese Unexamined Patent Publication Nos. 6-61489 and 6-120499.
To date, a-Si TFTs and p-Si TFTs have been widely used in display devices such as liquid crystal display devices and electroluminescent display devices (hereafter abbreviated as EL display devices). In addition, there is a prior-art technique for liquid crystal display devices and EL display devices in which, using p-Si TFTs, pixel TFTs and peripheral driver circuit TFTs are both formed on a glass substrate.
Where the channel region, the source region, and the drain region are made of the same kind of semiconductor, the dopant leaks and diffuses into the channel region during the heat treatment for activating a dopant contained in the source region and the drain region in the fabrication, reducing the effective channel region and degrading the performance of the TFT. Furthermore, in the cases of p-Si TFTs and p-SiGe TFTs, the dopant likewise leaks and diffuses into the channel region when a crystallization step is performed after the doping of the dopant.
In the case of a p-Si TFT, due to the fact that, in polycrystalline silicon, the dopant diffuses fast along the grain boundaries, the dopant contained in the source region and the drain region leaks and diffuses even more widely into the channel region. Further, in the case of a TFT in which a polycrystalline silicon thin film is used for the channel region, the OFF current is larger than that of a TFT in which an amorphous silicon thin film is used for the channel region. In order to control the OFF current, there are prior art techniques which involve the forming of a lightly doped drain (LDD) region, in which the dopant concentration is low, or the forming of a source region having a low dopant concentration and a drain region having a low dopant concentration.
In a TFT having an LDD region and a channel region composed of a polycrystalline silicon thin film, the LDD region, which is in contact with the channel region, has a low dopant concentration, and therefore, the amount of dopant that diffuses into the channel region is small. However, the resistance rate of a polycrystalline silicon thin film having a low dopant concentration is easily affected by the dopant concentration, and therefore, even if the amount of diffused dopant is small, the resistance value greatly varies, causing the additional problem of it being difficult to form an LDD region exhibiting a uniform concentration. In other words, in the TFT, a uniform parasitic resistance is difficult to obtain, and a large variation in the driving current is caused. This discussion is also applicable to a source region having a low dopant concentration.
In the case of p-SiGe TFTs, according to Japanese Unexamined Patent Publication Nos. 6-61489 and 6-120499, the temperature of the heat treatment during the fabrication can be reduced, and thereby the leaking and diffusing of the dopant into the channel region is reduced. However, as with the case where the channel region is formed of a polycrystalline silicon thin film, the OFF current increases. Moreover, in the case where polycrystalline silicon germanium is used for the channel region, the density of the crystal defect increases when compared to that in the case where polycrystalline silicon is used for the channel region, degrading the subthreshold characteristics.
Furthermore, where reduction of the sizes of a-Si TFTs, p-Si TFTs, and p-SiGe TFTs is necessary, the dopant diffusion more acutely affects the degradation of TFT characteristics since the width of the diffusion of the dopant into the channel region is invariable. Therefore, the proportion of the diffusion resistances of the source and drain regions to the parasitic resistance of the TFT increases, degrading the driving performance of the TFT. In addition, where it is necessary to ensure a certain channel length in the channel region in which the dopant is not diffused, the source region and the drain region must be made smaller. However, if the contact areas between the source region and the source electrode and between the drain region and the drain electrode are made smaller, the proportion of the contact resistance to the parasitic resistance increases.
In summary, the prior art TFT has the following problems. 1) When the channel region, the source region, and the drain region are formed of the same kind of semiconductor, the dopant concentration in a boundary portion of the source region adjacent to the channel region and that in a boundary portion of the drain region adjacent to the channel region are difficult to precisely control. 2) In particular, in application fields requiring high-speed driving characteristics such as in display devices, the channel region needs to be formed of a polycrystalline semiconductor, but the use of polycrystalline semiconductor for the channel region necessitates reduction in off-current by providing an LDD region. Therefore, if the dopant concentration cannot be precisely controlled, it is difficult to uniformly form TFTs having unvarying characteristics. 3) When a polycrystalline silicon germanium thin film is used for the channel region, it is possible to reduce the temperature of the heat treatment required in the fabrication process, but the subthreshold characteristics of the TFT tend to degrade.
In view of the foregoing and other problems of the prior art, it is an object of the invention to provide a TFT having a channel region composed of a first semiconductor, a source region comprising a first low melting point region composed of a second semiconductor having a melting point lower than that of the first semiconductor, and a drain region comprising a second low melting point region composed of a third semiconductor having a melting point lower than that of the first semiconductor, whereby the dopant concentrations of a first dopant contained in the boundary portion of the source region adjacent to the channel region and of a second dopant contained in the boundary portion of the drain region adjacent to the channel region are precisely controlled. It is a second object of the invention to provide a method of producing the TFT of the invention. It is a third object of the invention to provide a TFT array substrate comprising the TFTs made in accordance with the invention. It is a fourth object of the invention to provide a liquid crystal display device comprising the TFTs made in accordance with the invention. It is a fifth object of the invention to provide an EL display device comprising the TFTs made in accordance with the invention.
In order to accomplish the first object of the invention, there is provided a TFT formed on an insulating substrate, comprising: a channel region comprising a high melting point region composed of a first semiconductor; a source region being in contact with the high melting point region of the channel region, the source region comprising a first low melting point region composed of a second semiconductor having a melting point lower than that of the first semiconductor, and the source region containing a first dopant; a source electrode electrically connected to the high melting point region of the channel region via the first low melting point region of the source region; a drain region being spaced apart from the source region and in contact with the high melting point region of the channel region, the drain region comprising a second low melting point region composed of a third semiconductor having a melting point lower than that of the first semiconductor, and the drain region containing a second dopant; a drain electrode electrically connected to the high melting point region of the channel region via the low melting point region of the drain region; and a gate electrode electrically insulated from the channel region, the source electrode, and the drain electrode, the gate electrode controlling an electric field applied to the channel region.
This makes it possible to provide such a TFT that the boundary portion of the source region between the channel region and the source region and the boundary portion of the drain region between the channel region and the drain region have precisely controlled dopant concentrations.
In addition, it is made possible to enlarge, in comparison with the prior art, the effective channel region in which the dopant is not leaked or diffused, and accordingly, even with the scaling down of the size of a TFT is necessary, high performance of the TFT is ensured. The TFT in accordance with the present invention may be any of a planar TFT, a top gate staggered TFT, and a bottom gate staggered TFT. The term xe2x80x9cinsulating substratexe2x80x9d is intended to include a substrate having electrically insulative property and such a substrate that an electrically insulating film is formed on an arbitrary substrate. Note also that the term xe2x80x9cthe high melting point regionxe2x80x9d in the channel region is intended to mean a region composed of the first semiconductor having a melting point higher than those of the second semiconductor of the source region and the third semiconductor of the drain region.
The channel region may have the high melting point region in a portion thereof, but it is preferable that the channel region consist of only the high melting point region. The source region may consist of only the first low melting point region or may have the first low melting point region in a portion thereof. Specifically, the inside of the source region may have a layer of the second semiconductor. Likewise, the drain region may consist of only the second low melting point region or may have the second low melting point region in a portion thereof.
The second semiconductor and the third semiconductor may be any semiconductors as long as the melting points thereof are lower than that of the first semiconductor. Accordingly, the second semiconductor and the third semiconductor may be of the same semiconductor or may be of different semiconductors. When the second semiconductor and the third semiconductor are of the same semiconductor, the fabrication process is simplified, improving fabrication efficiency and reducing fabrication costs. Thus, it is possible to provide the TFT according to the invention at low cost.
Dopants are classified into two types, namely, acceptor dopants and donor dopants. When the first dopant and the second dopant are both acceptor dopants, an n-channel TFT is produced, whereas when both are donor dopants, a p-channel TFT is produced. As long as the first dopant and the second dopant are of the same type, they need not be the same dopant, but when the same dopant is used for both, the fabrication process is simplified, thereby improving fabrication efficiency and reducing fabrication costs. Thus, it is made possible to produce a TFT according to the invention at low cost.
When the first semiconductor of the channel region is a polycrystalline semiconductor, a TFT having excellent driving performance is provided. The driving performance of a TFT is primarily determined by the property of the first semiconductor which constitutes the channel region. Therefore, as long as the channel region is formed of a polycrystalline semiconductor, the source region may or may not be formed of a polycrystalline semiconductor. The drain region also may or may not be formed of a polycrystalline semiconductor as long as the channel region is formed of a polycrystalline semiconductor.
The discussion is now directed to melting points of the first semiconductor, the second semiconductor, and the third semiconductor. The melting point of a semiconductor varies depending on the semiconductor material that makes up the semiconductor and on the crystal structure. When the same semiconductor material is used, the melting point varies depending on the crystal structure, whereas when a plurality of the same semiconductors are used, the melting point varies depending on the composition ratio, the crystal structures thereof, and the like.
First, when a TFT is constructed such that the semiconductor of the source region and the third semiconductor of the drain region are composed of the same semiconductor material as that of the first semiconductor of the channel region but the crystal structure of the semiconductor material is different from that of the first semiconductor, precise control of the dopant concentration is reliably achieved. A specific example thereof is such a TFT that the first semiconductor is a polycrystalline semiconductor, and the second semiconductor and the third semiconductor are an amorphous semiconductor composed of the same semiconductor material as that of the first semiconductor.
Second, when a TFT is constructed such that each of the second semiconductor of the source region and the third semiconductor of the drain region comprises group IVB atoms and the same semiconductor material as that of the first semiconductor of the channel region, precise control of the dopant concentration is also reliably achieved. Preferable examples of the group IVB atoms are carbon (C), silicon (Si), and germanium (Ge). Specific examples of the TFT construction include the following: the first semiconductor is made of silicon and the second semiconductor and the third semiconductor are made of silicon and germanium; the first semiconductor is made of silicon and the second semiconductor and the third semiconductor are made of silicon, germanium, and carbon; and the first semiconductor is made of germanium and the second semiconductor and the third semiconductor are made of germanium and silicon. As long as the first semiconductor is a polycrystalline semiconductor, each of the second semiconductor and the third semiconductor may or may not be a polycrystalline semiconductor.
Each of the second semiconductor and the third semiconductor is not limited to a semiconductor in which the same semiconductor as that of the first semiconductor and the group IVB atoms are uniformly distributed, but the group IVB atoms may be unevenly distributed therein. For example, in the case where the same semiconductor material as that of the first semiconductor is uniformly distributed, the group IVB atoms may be distributed so that the concentration of the group IVB atoms is high in the vicinity of the surface and the concentration decreases toward the lower portion, or that the concentration of the group IVB atoms is high in a specific region and in the rest of the region, the concentration is low. A specific example of such a TFT may include such a TFT that each of the low melting point regions of the source and drain regions has, in a local region thereof, a germanium high concentration region in which the atomic density of germanium is higher than the rest of the source or drain region, and the germanium high concentration region of the source region is in contact with the channel region and the source electrode and the germanium high concentration region of the drain region is in contact with the channel region and the drain electrode.
Third, when a TFT is constructed such that the second semiconductor of the source region and the third semiconductor of the drain region consist of only a different semiconductor material from that of the first semiconductor and the third semiconductor, precise control of the dopant concentration is also reliably achieved. A specific example thereof includes such a TFT that the semiconductor material constituting the first semiconductor is silicon and the semiconductor material constituting the second semiconductor and the third semiconductor is germanium. When the first semiconductor is a polycrystalline semiconductor, the second semiconductor and the third semiconductor may or may not be a polycrystalline semiconductor.
The following construction is also possible: the second low melting point region of the drain region has a low concentration-doped drain region and a high concentration-doped drain region, the high concentration doped drain region having a dopant concentration higher than that of the low concentration-doped drain region and being connected to the channel region via the low concentration-doped drain region, and the drain electrode is in contact with the high concentration-doped drain region. This makes it possible to suppress degradation of OFF current characteristics of the TFT (increase in the OFF current of the TFT), even when the channel region is composed of a polycrystalline semiconductor. In addition, it is possible to provide, in a like manner, a low concentration-doped source region and a high concentration-doped source region in the first low melting point region of the source region.
In order to accomplish the second object of the invention, there is provided a method of producing a TFT comprising: forming a semiconductor thin film on an insulating substrate, the semiconductor thin film composed of a first semiconductor; patterning the semiconductor thin film by photolithography and etching to form a patterned semiconductor thin film; forming a first electrically insulating film so as to cover the patterned semiconductor thin film; subsequent to the step of forming a first electrically insulating film, forming a gate electrode on the patterned semiconductor thin film; implanting ions having group IVB atoms into a portion of the patterned semiconductor thin film to form a pair of low melting point regions on the patterned semiconductor thin film, the low melting point regions being spaced apart from each other and composed of a second semiconductor; doping the regions where the pair of the low melting point regions have been formed with a dopant to form a source region, a drain region, and a channel region, such that the source and drain regions are doped with the dopant and that the channel region is not doped with the dopant and is sandwiched between the source region and the drain region; forming a second electrically insulating film so as to cover the gate electrode; forming a source electrode and a drain electrode, the source electrode piercing through the first and second insulating films on the source region and being electrically insulated from the gate electrode, the drain electrode piercing through the first and second insulating films on the drain region and being electrically insulated from the gate electrode and electrically connected to the drain electrode; and heating the source region and the drain region at a predetermined temperature to activate the dopant contained in the source region and the drain region.
In comparison with the case where the channel region, the source region, and the drain region are formed of the same semiconductor, the heat treatment temperature can be reduced when activating the dopant contained in the source region and the drain region. Therefore, by the above-described method, the diffusion of the dopant into the channel region is suppressed, and it is made possible to provide a planar TFT in which the dopant concentrations are precisely controlled in the boundary portion between the channel region and the source region and in the boundary portion between the channel region and the drain region.
When the step of implanting group IVB atoms is carried out subsequent to the step of forming a gate electrode, the gate electrode may be used as a mask, simplifying the forming to a pair of regions having differing melting points in the patterned semiconductor thin film. Alternatively, the step of implanting group IVB atoms may be carried out prior to the step of forming a gate electrode by using a resist mask having a predetermined pattern. Further, the step of implanting group IVB atoms may be such that one kind of group IVB atoms is implanted or that a plurality of kinds of group IVB atoms are implanted. In this step, it is preferable that the ions having group IVB atoms be ions of a hydride of group IVB atoms. The group IVB atoms may be of carbon, silicon, or germanium. More specifically, monosilane (SiH4), germanium hydride (GeH4), methane (CH4), or the like may be employed for the source molecules. In addition, it is possible that the step of implanting group IVB atoms is repeated a plurality of times to implant a first group IVB atoms into one of the low melting point regions and a second group IVB atoms into the other low melting point region.
In another embodiment, in order to accomplish the second object of the invention, there is provided a method of producing a TFT, comprising: forming a first thin film composed of a third semiconductor on an insulating substrate; patterning the first thin film by photolithography and etching to form a source thin film and a drain thin film; doping the first thin film or the source and drain thin films with a dopant to form a source region in the source thin film and a drain region in the drain thin film, such that the source and drain regions are doped with the dopant; subsequent to the step of patterning a first thin film, forming a second thin film over the insulating substrate, the second thin film composed of a fourth semiconductor having a melting point higher than that of the third semiconductor; patterning the second thin film by photolithography and etching to form a channel thin film connecting the source thin film and the drain thin film; forming a first electrically insulating film so as to cover the source thin film, the drain thin film, and the channel thin film; subsequent to the step of forming a first electrically insulating film, forming a gate electrode above the channel thin film; forming a second electrically insulating film so as to cover the gate electrode; forming a source electrode and a drain electrode, the source electrode piercing through the first and second electrically insulating films so as to reach the source region and being electrically insulated from the gate electrode, the drain electrode piercing through the first and second electrically insulating films on the drain region so as to reach the drain region and being electrically insulated from the gate electrode; and heating the source region and the drain region at a predetermined temperature to activate the dopant contained in the source region and the drain region.
In comparison with the case where the channel region, the source region, and the drain region are formed of the same semiconductor, the heat treatment temperature can be reduced when activating the dopant contained in the source region and the drain region. Therefore, by the above-described method, the diffusion of the dopant into the channel region is suppressed, and it is made possible to provide a top gate TFT in which the dopant concentrations are precisely controlled in the boundary portion between the channel region and the source region and in the boundary portion between the channel region and the drain region.
In place of the step of forming the source and drain electrodes in the above method, it is possible to include a step of forming a source electrode and a drain electrode on the insulating substrate prior to the step of forming a first thin film and to form the source thin film above the source electrode and the drain thin film above the drain thin film in the step of patterning the first thin film. This achieves a top gate staggered TFT. In addition, in place of the step of forming a first thin film and the step of patterning the first thin film, it is possible to form the source thin film and the drain thin film by the steps of forming a third thin film composed of a fourth semiconductor on the insulating substrate, patterning the third thin film by photolithography and etching to form thin films spaced from each other, and implanting ions having group IVB atoms into the pair of thin films. This achieves a top gate staggered TFT.
In further another embodiment, in order to accomplish the second object of the invention, there is provided a method of producing a TFT comprising: forming a gate electrode on an insulating substrate; forming a first electrically insulating film so as to cover the gate electrode; subsequent to the step of forming a first electrically insulating film, forming a first thin film composed of a fifth semiconductor on the insulating substrate; patterning the first thin film by photolithography and etching to form a channel thin film above the gate electrode; forming a second thin film composed of a sixth semiconductor having a melting point lower than that of the fifth semiconductor; patterning the second thin film by photolithography and etching to form a source thin film and a drain thin film, the source and drain regions being in contact with the channel thin film and spaced apart from each other; doping the source thin film and the drain thin film with a dopant to form a source region and a drain region; forming a source and drain electrodes, the source electrode being electrically connected to the source region, the drain electrode being spaced from the source electrode and in contact with the drain region; and heating the source region and the drain region at a predetermined temperature to activate the dopant in the source region and the drain region.
Compared to the case where the channel region, the source region, and the drain region are composed of the same semiconductor, the treatment temperature can be reduced in activating the dopant contained in the source region and the drain region. Therefore, by the above-described method, the diffusion of the dopant into the channel region can be suppressed, and it is made possible to provide a bottom gate staggered TFT in which the dopant concentrations in the boundary portions between the channel region and the source region and between the channel region and the drain region are precisely controlled. In addition, because the treatment temperature can be reduced, the resistances of the source region and the drain region are sufficiently lowered even when the heating step, which is conventionally carried out using a heat treatment furnace, is performed using a rapid heating apparatus such as a lamp annealer. Moreover, by using the rapid heating apparatus, the throughput of fabrication can be remarkably improved.
In place of the steps of forming a second thin film and patterning the second thin film, it is possible to form the source thin film and the drain thin film by the steps of forming a third thin film composed of the fifth semiconductor, patterning the third thin film by photolithography and etching to form a pair of thin films spaced apart from each other and connected to each other via the channel thin film, and implanting ions having group IVB atoms into the pair of thin films to form a low melting point region composed of a sixth semiconductor having a melting point lower than that of the fifth semiconductor. This achieves a bottom gate staggered TFT.
The following are commonly applicable to the fabrication methods of a planar TFT, a top gate staggered TFT, and a bottom gate staggered TFT.
When a step of crystallizing the semiconductor which forms the channel region is included in the methods described above, a TFT having high driving performance is produced. As long as the channel region is subjected to the step of crystallizing, the semiconductors of the source region and the drain region may be polycrystallized. It is noted that when the semiconductor of the channel region is polycrystallized, the OFF current characteristics of the TFT are lowered.
However, it is possible to include, subsequent to the step of doping, the step of additionally doping a portion of the drain region with a dopant to form a low concentration-doped drain region and a high concentration-doped drain region, the low concentration-doped drain region having not been subjected to the additional doping and in contact with the channel region, the high concentration-doped drain region having been subjected to the additional doping having a dopant concentration higher than the low concentration-doped drain region. This suppresses degradation of the OFF current characteristics of the TFT, even when the channel region of the TFT is formed of a polycrystalline semiconductor.
In the step of heating, the heat treatment temperature for activating the dopant may be 600xc2x0 C. or lower so that the deformation of the substrate in the heat treatment is suppressed even when a glass substrate is used as the insulating substrate. This widens the choice of the substrate.
In order to accomplish the third object of the invention, there is provided a TFT array substrate comprising an insulating substrate; a plurality of thin film transistors according to the present invention, the thin film transistors formed on the insulating substrate, a source line electrically connected to the source electrode, a drain line electrically connected to the drain electrode, and a gate line electrically connected to the gate electrode.
By employing the above-described construction, it is made possible to provide a TFT array substrate in which high performance TFTs are arranged with good flatness. In addition, since the TFTs according to the invention are employed and the heat treatment temperature is thereby reduced, it is made possible to provide a TFT array substrate having a TFT array formed on a glass substrate with good flatness. This allows a wider choice of the substrate.
When the TFTs employed in the array substrate are such that the the channel region consists of only the high melting point region, the high melting point region being composed of polycrystalline silicon, the source region consists of only the first low melting point region, the first low melting point region being composed of polycrystalline silicon germanium, and the drain region consists of only the second low melting point region, the second low melting point region being composed of polycrystalline silicon germanium, the array substrate has improved performance over those employing conventional p-Si TFTs and p-SiGe TFTs.
In order to accomplish the fourth objection of the invention, there is provided a liquid crystal display device comprising an insulating substrate, a TFT according to the invention formed on the insulating substrate, a source line electrically connected to the source electrode, a drain line electrically connected to the drain electrode, a gate line electrically connected to the gate electrode, a display electrode formed on a surface of the insulating substrate and electrically connected to the drain line, a first liquid crystal alignment film covering the thin film transistors the source line, the drain line, the gate line, and the display electrode, an opposing substrate opposing the insulating substrate, an opposing electrode formed on the opposing substrate and opposing the display electrode, a second liquid crystal alignment film formed on the opposing substrate and covering the opposing electrode, a liquid crystal layer being in contact with the first liquid crystal alignment film and the second liquid crystal alignment film and sandwiched between the insulating substrate and the opposing substrate; and a sealing portion for sealing the liquid crystal layer, the sealing portion provided at a peripheral region of the insulating substrate and the opposing substrate.
In the device construction as described above, an insulating substrate on which small-sized, high performance TFTs are arranged with high precision is employed, and therefore, a high display speed liquid crystal display device having a high aperture ratio or a high pixel resolution is achieved. The TFT according to the invention may be employed for the pixel TFTs and/or the peripheral driver circuit TFTs.
When the TFT employed in the liquid crystal device is such that the channel region consists of only the high melting point region composed of polycrystalline silicon, the source region consists of only the first low melting point region composed of polycrystalline silicon germanium, and the drain region consists of only the second low melting point region composed of polycrystalline silicon germanium, the liquid crystal display device has improved performance over those employing conventional p-Si TFTs and p-SiGe TFTs.
In order to accomplish the fifth object of the invention, there is provided an EL display device comprising an insulating substrate, a TFT according to the invention formed on the insulating substrate, a source line electrically connected to the source electrode, a drain line electrically connected to the drain electrode, a gate line electrically connected to the gate electrode, a display electrode formed on a surface of the insulating substrate, an opposing electrode opposing the display electrode, and a light-emitting layer formed between the display electrode and the opposing electrode.
In the device construction as described above, an insulating substrate on which small-sized, high performance TFTs are arranged with high precision is employed, and therefore, a high display speed EL display device having a high aperture ratio or a high pixel resolution is achieved. The TFT according to the invention may be employed for the pixel TFTs and/or the peripheral driver circuit TFTs.
When the TFT employed in the EL display device is such that the channel region consists of only the high melting point region composed of polycrystalline silicon, the source region consists of only the first low melting point region composed of polycrystalline silicon germanium, and the drain region consists of only the second low melting point region composed of polycrystalline silicon germanium, the EL display device has improved performance over those employing conventional p-Si TFTs and p-SiGe TFTs.